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Product Overview
(R)
Integrated Circuits Group
ID246 Series
Flash Memory Card
(Model Numbers: ID246xxx)
Spec No.: CPS0008E-001
SHARI=
ID246 SERIES PRODUCT
OVERVIEW
l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.
l When using the products covered herein, please observe the conditions written herein and the precautions
outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2). even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics . Instrumentation and me.asuring equipment * Machine tools * Audiovisual equipment . Home appliances * Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trams, automobiles, and other transportation equipment . Mainframe computers - Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment . Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following performance in terms of functionality, * Aerospace equipment . Communications equipment for trunk lines . Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. equipment which demands extremely high
reliability, or accuracy.
l Please direct all queries regarding the products covered herein to a sales representative of the company.
CPS0008E-00
SHARP
ID246 SERIES PRODUCT OVERVIEW
2
Contents
P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. P. 3 3 4 5 6 7 7 8 9 9 12 12 12 12 12 15 17 18 21 22 22 22 22 22 23 25 25 27 33 34 35 36 36 37
1. Intnxluction ................................................................................................................. 2. Features ....................................................................................................................... 3. Block Diagram ............................................................................................................ 4. Pin Connections .......................................................................................................... 5. Signal Description ...................................................................................................... 6. Functions ..................................................................................................................... 6. 1 6. 2 6. 3 Common Memory.. ......................................................................................... Attribute Memory ................ ...........................................................................
Function Table ..... . .......................................................................................... 7. Card Information Structure (CIS) ............................................................................... 8. Card Control ............................................................................................................... 8. 1 8. 2 8. 3 8. 4 Reset ............................................................................................................. Status Register ................................................................................................
Write Protect Switch ....................................................................................... Identifier Codes. ..............................................................................................
9. Component Management Register (CMR) ................................................................. 10. Commad Definitions.. ............................................................................................... 10. 1 Query Command.. ....... .................................................................................... lo. 2 STS Configuration 11. Electrical Specifications Command ........................................................................ .............................................................................................
11. 1 Absolute Maximum Ratings ........................................................................... 11. 2 Recommended Operating Conditions. ............................................................ 11. 3 Capacitance ..................................................................................................... 11. 4 AC Input/Output 12. DC Characteristics 13. AC Characteristics Test Conditions .................................................................. ...................................................................................................... ......................................................................................................
13. 1 Common Memory Read Operations ............................................................... 13. 2 Command Write Operations : Common Memory .......................................... 13. 3 Attribute Memory Read Operations ............................................................... 13. 4 Attribute Memory Write Operations .............................................................. Down.. ................................................................................ 14. Specification Changes ................................................................................................ 15. Other Precautions.. ...................................................................................................... 16. External Diagrams ...................................................................................................... 13. 5 Power-Up/Power
SHARP
1. Introduction
ID246 SERIFS PRODUCT OVERVIEW
This datasheet is for SHARP's ID246 series flash memory card. This datasheet provides all AC and DC characteristics (including timing waveforms) grated registers(including and a convenient reference for the device command set and the cards intethe Flash Memory's status registers). This datasheet provides description of the meth-
ods which are very helpful for customer to use the card.
2. Features
2.1 2.2 Type Overview ID246Pxx Common Memory Capacity Device Attribute Memory Capasity Supply Voltage Access time Erase Unit Program/Erase Cycles External Dimensions
Byte
Flash Memory Card
ID246Rxx 40Mbyte 20Mword LH28F032SKD lodevices
ID246Sxx 48Mbyte 24Mword LH28F032SKD 12devices
32Mbyte 16Mword LH28F032SKD 8devices
Word
(Note:standard
2Kbyte CIS is not writable)
vcc=sv ! vpp=sv, vcc=3.3v I vpp=3.3v,5v 150ns(@Vcc=%) 250ns(@Vcc=3.3v) 64K word blocks 1OO,OOOcycles/Block PCMCIA Type 1 54.0X 85.6X 3.3mm
2.3 2.4 2.5 2.6
Interface Function Table Pin Connections Type of Connector
Parallel I/O Interface See Function Table in page. 9 See Pin Connections in page. 5 Conforms to PCMCIA PC Card Standard 95 Card Use Connector Card connector: JC20-J68S-NB3 FCN-568J068-G/O ICM-C68S-TS by JAE by Fujitsu 13-5035A by JST or or
2.1 2.8 2.9
Operating Temperature Storage Temperature
0 to 60C -20 to 65C
Not designed for rated radiation hardened.
SHARP
3. Block Diagram
ID246 SERIES PRODUCT
OVERVlEW
Control Logic
Flash Memory
lw
+
l
cE#
wE#
Data * Add +
RP#-+
-
-
*
OE#
STS ---( '
VPP2
/A
/I wFJ# cE# wE# OE# 4--4--4---(c 4i()-I I ' - - -VPP 1 t vcc t Data *' Add 4 RPWJ STS -
vcc t Flash Memory
b Data b Add ** STS
zvcc
VPPl VPP2 . ~
:: ::
: . m
VPP2
vcc
'
Flash Memory 3 e -Rp# Data Add STS wP#k+ cE#l* wE# 4---, OE# M -bwP# + cm *WI3 OE#
Flash Memory .
A -
Figure 1. Block Diagram
SHARP
4. Pin Connections
Table 1. Pin Connections
ID246 SERIES PRODUCT OVERVIEW
5
I;r I
SIGNAL
I
I/O
I
FUNCTION
5
D6 D7
6 7 8
CEI# AIO
9 OE# 10 Al1 1 11 1As
I/O I/O I I I I II
Data Bit 6 Data Bit 7 Card Enable 1 Address Bit 10 Output Enable Address Bit 11 IAddress Bit9
4
ACTIVE
II
;,"
I
T
SIGNAL
I
I/O
I
FUNCTION
ACTIVE
LOW
I
I
39 40 41 42 43 44
DIG ~D,J DIG CEz# VSI# RFU
I
1 I/O 1 I/O I/O I 0 1
I I 45 Imu
IData Bit 13 IData Bit 14 Data Bit 15 Card Enable 2 Voltage Sense 1 Reserved IReserved
I
LOW
I
1
1
15 IWE# I 16 IRDYTSSY# 17 vcc 18 VPPI
I I I Write Enable I o IReady BUSY Supply Voltage Program Voltage
LOW
1 1 50 IAx
I I I 1Address Bit 20 I I IAddress Bit 21
I
1 22 23 24 25 26
IA7
As As A4 As
I I IAddress Bit7 I Address Bit 6 I Address Bit 5 I Address Bit 4 I [Address Bit 3
1 1 56 IA25 1 1 57 IVS2# 1 1 58 IkESET
I 1 (Address Bit 25 I 0 IVoltage Sense 2 I I (Reset
HIGH
LOW
-II
I 30 (Do I I/O (Data Bit 0 1 34 (GND I 1Ground
62 (BVD2 63 IBVD~
I0
Battery Voltage Detect 2 1
1 I/O (Data Bit 8
LOW
1 1 68 (GND
I
(Ground
T1003-01
I
CPSOQ08E.001
SHARP
5. Signal Description
Table 2. Signal Description
ID246 SERIES PRODUCT OVERVIEW
6
1
Function 40425 ,,. I :Ei#,CEz# >E# NE# Pull-down (250kn @Vcc=Sv) ADDRESS INPUTS: These are address bus lines which enable direct addressing of memory on the card. Signal Ao is not used in word access mode. DATA INPUT/OUTPUT Do through DIG constitute the bi-directional data bus. Drs is the most significant bit. CARD ENABLE 1 & 2: CEI# enables D+D7, CE2# enables Da-DIG. OUTPUT ENABLE: Active low signal gating read data from the memory card. WRITE ENABLE: Active low signal gating write data to the memory card. READY/BUSY OUTPUp Indicates status of internally timed erase or write activities. ID246 series has two types of Ready/Busy output mode; PCMCIA mode and High-Performance mode. In PCMCIA mode, a high output indicates the memory card is ready to accept accesses. A low output indicates that a device in the memory card is busy. In High-Performance mode, the card outputs low when the card is in default state. A high output indicates at least one of flash memory devices in the card comes to be ready to accept accesses. CARD DETECT 1 & 2: These signalsprovide for card insertion detection. The signalsare connectedto groundinternally on the memory card, andwill be forced low whenevera cardis placedin the socket.The host socketinterface circuitry shall supply 10K or larger pull-up resistorson thesesignal pins.
h-D15
IDYlBSY#
0
:DI#, CDz#
0
Pull-down Of2
VP (PPI.VPP2 [cc
iND
o t
WRITE PROTECT: Low:PuIl-down On Write Protect reflects the statusof the Write Protect switch on the High:Pull-up 1OOkn memorycard. WP setto high = write protected. I WRITE / ERASE POWER SUPPLY 1 & 2: CARD POWER SUPPLY: GROUND: REGISTER SELECT: Providesaccess attribute memory when REG# is low. to RESET Active high signalfor placingcard in Power-On Default State. I I I
EG# ESET ;VDI, BVDz 0 I Pull-up 1ookQ
'Sl#,
vs2#
o VSI#: Pull-down VS2#: N.C. I
BATTERY VOLTAGE DETECT 1 & 2: Thesesignalsarepulled high to maintainSRAM card compatibility. VOLTAGE SENSE1 & 2: Notifiesthe hostsocketof the CIS'sVCC requirements.VS~# pulledis lawn to ground when using the standard CIS, that indicate 3.3V operating available. is RESERVEDFOR FUTURE USE
T1172E.01
CPS0008E40'
SHARI=
6. Functions
6.1 Common Memory 6. 1. 1 Common
ID246 SERIES PRODUCT OVERVIEW
7
Memory Architecture
Figure 2 shows common memory architecture of ID246 series flash memory card. Device pair is consisted of two pieces of flash memory devices. Each device has individually erasable and lockable blocks. All blocks are divided into odd bytes and even bytes. Each device pair and block is selected by address bits. Table 3 shows definitions of address bits.
DEVICE PAIR 5 DEVll 1 DEVIO
/ / /
/'
Blodc63 1 I I I ``I W `I I I I
= = =
DEVICi PAIR 2 DEVS 1 DEV4 DEVIti PAIR 1 DEV3 1 DEV2 I DEVICE PAIR 0 LH28FO32SKD LH28FO32SKD - jGx-8&- - -4;I z 8jjii DEVl DEVO
/
/
Bank1 Bank0
1
Bank1 Bank0 1
F1076E4)'
ODD
EVEN yte Mode Word Mode Byte Mode
Word Odd-Byte
Mode Mode I\1 D15-D8
D7-DO
Figure 2. Common Memory Architecture
Table 3. Address Difinitions Address Pifinitions Select Even / Odd byte in the byte access mode. Select address in the block. Select a block. Select a bank Select a device pair. A16-Al A21 -A17 32MB ,4OMB ,48MB A0 (64KJ3/Block) (32blocks/bank)
A22 (2banks/device) A25 -A23
T1173E-01
SHARI=
6. 1.2 Erase
ID246 SERIES PRODUCT
OVERVIEW
8
Erase is executed one block at a time. Erasable block size is 64K bytes in byte access mode and 128K bytes in word access mode. 6. 1.3 Address Decoding
The higher address area of ID246 series flash memory card which goes beyond common memory area is not decoded in common memory access. It means that the system will access to random memory address of the memory card even if system will try to access to the memory address which exceeds memory capacity of the card. Please do not access to the memory address which goes beyond memory capacity of the card. As an enhanced function, the memory card enables to output invalid data (either of OOOOhor FFFFh) when system will access to the memory address which exceeds memory capacity of the card. Please contact our sales & marketing support to find concrete way of setting.
6.2
Attribute
Memory
Figure 3 shows attribute memory map of ID246 series flash memory card. Attribute memory is contained within the Card Control Logic. Attribute memory contains the Card Information Structure (CIS) and Component Management Registers (CMRs). The CIS contains tuple information and is located at even byte addresses beginning with address OOOOh(Please refer to section 7). The standard CIS of ID246 series flash memory card is hardwired and is for read only. As an enhanced function, the hardwired CIS area is switchable to EEPROM so that customer can program required CIS. Please contact our sales & marketing support to find concrete way of setting. The CMRs are located at even byte addresses beginning with address 4000h (Please refer to section 9).
,-"--'
T--"-`,
Address
ODD
EVEN
F1003-01
Figure 3. Attribute Memory Map
SHARP
6.3 Function
6.3.1 Common
ID246 SERIES PRODUCT
OVERVIBW
Table
Memory Access tcess
Table 4. Common Memory Mode Stand-by Byte Read Word Read Odd Byte Read Byte Write Word Write Odd Byte write
H H H
H L L
L L H
H X X
H H H
L L L
Don't care Odd Odd
Odd Even Don't care
6.3.2 Attribute Memory Access Table 5. Attribute Memory Access Mode Stand-by Byte Read Word Read Odd Byte Read Byte Write Word Write Odd Byte write REG# X L L L L L L L L CE,# H H H L L H H L L CE,# H L L L H L L L H A, X L H X X L H X X OE# X L L L L H H H H WE# X H H H H L L L L D,,, High-Z High-Z High-Z xx xx Don't care Don't care Don't care Don't care D 7-o High-Z Even xx Even High-Z Even Don't care Even Don't care
TS1059E-02
XX:Output data is invalid. The standard CIS is for read only. Write operation is only for CMRs and CIS on EEPROM
7. Card Information
Structure
(CIS)
The CIS is contained within attribute memory (Please refer to section 6.2). Table 6 shows standard CIS tuples, but it is for read only. As an enhanced function, the hardwired CIS area is switchable to EEPROM so that customer can program required CIS. Please contact our sales & marketing support to find concrete way of setting.
SHARP
1 Address 1 Value 1 OOh 1 Olh
ID246 SERIES PRODUCT
OVERVIEW
Table 6. Standard CIS
, 02h -1 / 04h
Rash Memory Access Time 150ns I
1 46h
Address 1 Value 1 Description 1 53h ISProduct Info 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 6Xh 6Ah 6Ch 48h H 41h A 52h R 50h P OOh END TEXT 4Yh I 4th 32h 34h 53h 52h D 2 4 S R
I I
II
08h 10h 12h
7Eh 9Eh
Capacity 32MB 40MB
02h 57h
Conditions 3Vcc Flash Memory Access Time 250ns Capacity 32MB 40MB 48MB End of Tuple
20h SPACE OOh ENDTEXT 53h S :Maker Info 48h 41h H A
52h R 1 50h IP 1 20h ISPACE 43h C 4I=h 0 1 52h IR I 50h IP 1 4Fh 0 i 52h IR ( 41h A 1 54h IT 49h I 4I=h 0 4Eh N OOh END TEXT PFh End of Tuple 1Ah Configuration Info 05h Tuple Link Last Index of Configuration Table
I
I
1Ch 1Eh
04h Tuple Link ( 1Ph IROM Access Time 200ns Capacity 2KB End of Tuule
I
I
6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah
28h 2Ah 1 2Cb 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h
05h Tuple Link 1 02h IConditions 3Vcc 1 1Ph ROM 2Ab Access Time 2OOr-r~ Olh PI% 18h 02h BOh DOh OOh 15h 23h 04h Olh Capacity 2KB End of Tuple JEDEC Code ID Tuple Link Manufacture Code Device Code End of Tuple Version Info Level 1 Tuple Link Major Version Minor Version
CPS0008E401
SHARP
Address
ID246 SERIES PRODUCT
OVERVIEW
Table 8. Standard CIS (Continued) 9Ah 9Ch 9Eh AOh A2h A4h A6h A8h AAh 1 Value 1 Description 08h Tiple Link Olh
02h
I
Index
vcc & vpp 79h Parameter Selection 55h Vcc Voltage 5V ICCStatic ICCAverage ICCPeak ICCPowerdown I
OCh 06h 06h 23h
ACh 1 1Bh 1 ContieurationTableEntrv 2 AEh 09h Tuple Link 02h Index BOh B2h B4h B6h B8h BAh Olh 79h B5h Vcc Onry Parameter Selection Vcc Voltage 5V
BCh BEh COh 1 1Bh (ICCPowerdown C2h 1Eh Device Geometry C4h 06h Tuple Link C6h 1 02h Bus C8h 1 llh IErase CAh ) Olh IReadsize CCh CEh DOh D2h D4h 1 Olh Write size Olh Partation: lblock 01 h Non-interleaved 20h ManufacturerID 04h ITunle Link Manufacturer Code
1Eh OCh ICCStatic 7Dh ICC Average 7Dh ICC Peark
I
I
I
-+E-ta
DEh EOh E2h E4h E6h 21h 02h 0 1h OOh FFh
Function Identification Tuple Link Function: MEMORY System:None End of CIS
I
CPS0008E-00
SHARP
8. Card Control
8. 1 Reset
ID246 SERIES PRODUCT OVERVIEW
12
The card is in initial state directly after power-up. make sure to initialize the card.
But we recommend to do reset operation after power-up
to
During block erase, byte write, or lock-bit configuration modes, an active RESET will abort the operation. RDYI BSY# remains low until the reset operation completes. Memory contents being altered are no longer valid; the data may be partially erased or written. The host must wait after RESET goes to logic-Low write another command, as determined by tpt.nvL. It is important to assert RESET to the card during a system reset. If a CPU reset occurs without a card reset, the host will not be able to read from the card if that card is in a different mode when the system reset occurs. For example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt to read code from the card, but will actually read status register data. Sharp's ID246 Series Flash Memory Card allows proper card reset following 8. 2 Status Register a system reset through the use of the RESET input. (VIL) before it can
Each flash memory device in the card has status register. The status register may be read to determine when a write, block erase, or lock-bits configuration is complete, and whether that operation completed successfully (please refer to Table 7). It may be read at any time by writing the Read Status Register command (70h, 7070h) into the CUI. In word access mode, the status register data of even byte devices are output to D7-0,and the status register data of odd byte devices are output to D15-8.
8. 3
Write Protect Switch
The ID246 Series Flash Memory Card has a write protect switch on the back of the card. When the switch is in the write protect position, the card blocks all writes to the common and attribute memory without Card Management Registers region (see Figure 4 ). 8.4 Read Identifier Codes / Block Status Code Manufacture Code and Device Code are contained within each flash memory device in the memory card. The identifier code operation is initiated by writing the Read Identifier Codes command (90h, 9090h) into the CUI of each memory device. The specific address of each device is necessary to be selected to read these codes (Table 9).
Writeble position r I Write pro=sition
Note: The write protect switch is shown by the black square.
Figure 4. Write Protect Switch
CPSo@XEi)ol
SHARP
Table 7(a). WSMS 7
ID246 SERIES PRODUCT OVERVIEW
13
Status Register Definition BESS 6 1 ECBLBS 5
STATUS Check RY/BY# pin or SR.7 to determine block erase, full chip erase, (multi) word/byte write or block lock-bit configuration completion. SR.6-0 are invalid while SR.7="0" If both SR.5 and SR.4 are "1"safter a block erase. full chip erase,(multi) word/bite write, block lock-bit configuration or STS configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of VPP level. the WSM interrogates and indicates the VPP level only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. SR.3 is not guaranteed to reports accurate feedback only when vPPi=vPPn 1. SR. 1 does not provide a continuous indication of block lock-bit values. The WSM interrogates block lock-bit, and WP# only after block erase, full chip erase, (multi) word/byte write or block lock-bit configuration command sequences. Itinforms the system, depending on the attempted operation, If the block lock-bit is set and/or WP# is not VIH. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock-bit status. SR.0 is reserved for future use and should be masked out when polling the status register. TllfnC~n,
1 WSBLBS 4
VPPS 3
NOTES:
wss 2
DPS 1
R 0
SR.7 = WRITE STATE MACHINE 1 = Ready 0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS 1 = Error in Erase or Clear Block Lock-Bits 0 = Successful Erase or Clear Block Lock-Bit 5R.4 = WRITE AND SET BLOCK LOCK-BIT 1 = Error in Write or Set Block Lock-Bit 0 = Successful Write or Set Block Lock-Bit SR.3 = VP? STATUS 1 = VPP Low Detect, Operation Abort
0 = VPP OK
STATUS
3R.2 = WRITE SUSPEND STATUS 1 = Write Suspended 0 = Write in Progress/Completed jR. 1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit and/or WP# Lock Detected, Operation Abort 0 = Unlock 3R.0 = RESERVED FOR FUTURJZ ENHANCEMENTS
7
6
5
4
3
NOTES:
2
1
0
XSR.7 = STATE hlACHINE STATUS 1 = Multi Word/byte Write available 0 = Multi Word/byte Write not available XSR.QO=RESERVED FOR FUTURE ENHANCEMENTS
After issue a Multi Word/Byte Write command: XSR.7 indicates that a next Multi Word/Byte Write command is available. XSR.B-0 is reserved for future use and should be masked out when oolline the extended status register.
SHARP
Table 8.
ID246 SERIES PRODUCT OVERVIEW
14
Identifier Codes / Block Status Select Device-pair k%1 Address in Device hiA, ooooOh OCOOlh 00002h 00003h Even/Odd A0 0:Even 1:Odd 0:Even 1:Odd Data Output D,-D, 32MB ,4OMB, 48MB BOh DOh Block Status Code D,: O=Unlocked, l=Locked D,: O=Last Erase operation completed successfully l=Last Erase operation did not completed successfully D,-D,: Reserved
Tl 1MEOl
Manufacture Identifier Code Device Identifier Code
DPA DPA
Block Status Code
DPA
XOOO4h XOOO5h (X: Select Block)
0:Even 1:Odd
NOTE: A,, is ignored in word access mode, and D,5-D, outputs the Odd byte data. DPA: Address as select device pair BLKD: Block Lock Configuration Data MLKD: Master Lock Configuration Data
SHARP
9. Component
attribute memory.
ID246 SERIES PRODUCT
OVERVIEW
Management
Registers
(CMR)
Component Management Registers (CMR)
are mapped at even byte locations beginning at address 4000h in
9. 1
Configuration Address 4000h
Option Register Bit.7 SRESET SRESET: Bit.6
(Address:4000h) Bit.5 Bit.4 Bit.3 Reserved Bit.2 Bit. 1 Bit.0
l=Reset State O=End Reset Cycle
9. 2
Card Configuration Address 4002h Bit.7
Register
(Address:4002h) Bit.5 Reserved Bit.4 Bit.3 Bit.2 PWDN Bit. 1 Reserved Bit.0
Bit.6
PWDN:
l=Power-Down Device pairs that apointed by Sleep Control Register(4118h-411 Ah) are in PowerDown. O=Power-Up
9. 3
Socket and Copy Register Address 4006h Bit.7 Reserved
(Address:4006h) Bit.6 Bit.5 Copy No. Bit.4 Bit.3 Bit.2 Bit.1 Bit.0
Soket No.
Soket No.: Socket Number Copy No.: Copy Number
I
9. 4 Address 4100h
The card may use to distinguish between similar cards installed in a system.
TlOL-01
Card Status Register Bit7 ADM
(Address:41 Bit.6 ADS
OOh) Bit.5 SRESET Bit.4 CMWP Bit.3 PWDN Bit.2 CISWP Bit.1 WP Bit.0 RDYIBSY
ADM: ORed value of the Ready/Busy Mask Register. 1 = Any device is masked. 0 = All Devices are not Masked. ADS: ORed value of the Sleep Control Register. 1 = Any device-pair is Controled power-down by bit.2 of the Card Configuration Register. SRESET: Reflects the bit.7 of the Configuration Option Register. CMWP: Reflects the bit.1 of the Write Protection Register. PWDN: Reflects the bit.2 of the Card Configuration Register. CISWP: Reflects the bit.0 of the Write Protection Register. WP: Indicates the Write Protect Switch status. 1 = Write Protect Switch: ON 1 = Write Protect Switch: OFF RDY/BSY: Reflects the Ready/Busy StatusRegister. 1 = All devices are READY. 0 = Any device is BUSY.
TIO54-01
SHARP
9. 5 Write Protection Register Address 4104h BLKEN: Bit.7
ID246 SERIES PRODUCT OVERVIEW
16
(Address:41 Bit.6
04h) Bit.5 Reserved Bit.4 Bit.3 Bit.2 BLKEN Bit. 1 CMWP Bit.0 CISWP
Block Locking Enable 1 = Enable Block Locking 0 = All Block Unlocked Common Memory Write Protect CMWP: 1 = Common Memory without CIS region in Write Protect Status Common Memory CIS Write Protect CISWP: 1 = Common Memory CIS in Write Protect Status
TI 176E4l
9. 6
Sleep Control Register Address 411Al-l 4118h Bit.7
(Address:41 Bit.6
18h-411 Ah) Bit.5 DEV 10/l 1 Bit.4 DEV8/9 Bit.3 Reserved DEV6/7 Bit.2 DEV4/5 Bit. 1 DEV2J3 Bit.0 DEVO/l mode
TIW741
Reserved
l= Select sleep mode device-pair If set to "I", the corresponding device-pairs are putted into deep powerdown by PWDN bit of Configuration Status Register.
9. 7
Ready/Busy Address 4122h 4120h
Mask Register Bit.7 DEV7
(Address:41 Bit.6 Reserved DEV6
20h-4122h) Bit.5 Bit.4 1 DEV4 Bit.3 DEVll DEV3 Bit.2 DEVlO DEV2 Bit.1 DEV9 DEVl Bit.0 DEV8 DEVO
DEVS
1 =Mask the Rdy/Bsy# The corresponding device's Rdy/Bsy# signals to set bit are ignored for cards RDY/BSY# output.
9. 8
Ready/Busy Address 413231 4130h
Status Register Bit.7
(Address:41
30h-4132h) Bit.4 Bit.3 DEVI 1 DEV4 DEV3 Bit.2 DEVIO DEV2 Bit. 1 DEV9 DEVl Bit.0 DEV8 DEVO
Bit.6 Reserved DEV6
Bit.5 DEVS
DEV7
l=READY O=BUSY Each bit indicates the corresponding device's Rdy/Bsy# signal.
TlOIlOl
9.9
Ready/Busy Address 4140h
Mode Register Bit.7 RACK:
(Address:41 Bit.6
40h) Bit.5 Reserved Bit.4 Bit.3 Bit.2 Bit.1 RACK Bit.0 MODE
MODE:
Ready Acknowledge Bit Must clear this bit after receiving ready status to prepare for next device's ready transition. RDY/BSY# Mode 1 = High-Performance Mode 0 = PCMCIA Mode
TIMSOL
SHARP
10. Command Definitions
ID246 SERIES PRODUCT OVERVIEW
Device operations are determined by writing specific commands to the Command User Interface. Table 9 defines the commands.
Table 9. Command Definitions
Read
Identifier
Codes
Word/Byte
Write
Level-Mode for Erase (RY/BY# Mode) STS Configuration Pulse-Mode for Erase STS Configuration Pulse-Mode for Write STS Configuration Pulse-Mode for Erase Address IA WA BA DA =Identifier =Write =Block =Device =Data read
and
Write write Write DA DA DA B8h (BSBSh) B8h (BSBSh) B8h (BSBSh) Write Write Write DA DA DA Olh (OlOlh) 02h (0202h) 03h (0303h) T115oE-m
and
Write Data
Write
cede Address Address Address
Address
ID WD SRD
=IdentiIier =Write =Data =Quety Data from
Codes
Status
Register
QA
Offset
Address
QD
Note:
1. Following
from Query database
the Read Identifier Codes command, read operations access manufacture, device, block status codes. 2. Status Register may be read to determine when a write, block erase, or lock bit configuration is complete, and whether that operation completed successfully. 3. If the block is locked, block erase or write operations are desabled.
4. Following command
the Third `DOH'.
Bus Cycle,inputs
the write address and write data of `N'+l
times.Finally,
input the confirm
CP%008E40
SHARP
10.1 Query Command
ID246 SERIES PRODUCT
OVERVIEW
Query database can be read by writing Query comman d (98H). Following address shown in Table 1 l-15 retrievethe critical information component. In word mode, Ds-Dis output the Query data of odd Byte Devices. Table 10. Example of Query Structure Output Offset Address (A6 - Al)
the command write, read cycle from
to write, erase and otherwise control the flash
T
A0
0 = Even 1 = Odd
output
%-D* High-z
High-Z High-Z High-Z
I
"Q" "Q"
"R" "R"
D,-Do
A,, A,, A,, A,, A,, A,
X8 mode 1 , 0 , 0 , 0 , 0 , 0 (20H) 1 , 0 , 0 , 0 , 0 , l(21H) 1 ,o,o,o, 1 ,oGw 1,0,0,0,1,1(23H) A,, A,, A,, A,, A, l,O,O,O,O (10H) 1 ,O,O,O,l (11H)
Xl6 mode
X
"Q"
"R"
"Q"
"R"
TllSZE-01
10. 1. 1 Block Status Register This field provides lock configuration and erase status for the specified block. These informations are only available when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status bit will be set to "l",this Table 11. block is invalid.
Query Block Status Register Length OlH Description Block Status Register DO : Block Lock Configuration O=Block is unlocked l=Block is locked Dl : Block Erase Status O=Last erase operation completed successfully l=Last erase operation not completed successfully D2-7: Reserved for future use
T1153E41
Offset (Word Address) (B A+2)H
NOTE: l.BA=The
beginning of a Block Address.
SHARI=
10. 1.2 CFI Query Identification The Identification
ID246 SERIES PRODUCT
OVERVIEW
19
String
String provides verification that the component supports the Common Flash Interface specifiIf indicates which version of the spec and which Vendor-specified command set(s) istare)
cation. Additionally, supported. Table 12.
CR Query Identification
Length 03H 02H 02H 02H 02H
String
Description Query Unique ASCII string "QRY" 5 lH,52H,59H Primary Vendor Command Set and Control Interfase ID Code OlH,OOH (SCS ID Code) Addressfor Primary Algorithm Extended Query Table 3 lH,OOH (SCS Extended Query Table Offset) Alternate Vendor Command Set and Control Interfase ID Code OOOOH (OOOOH means that no alternate exists) Address for Alternate Algorithm Extended Query Table OOOOH (OOOOH means that no alternate exists)
T1154E-01
Offset
(Word Address) lOH.1 lHJ2H 13H,14H 15HJ6H 17HJ8H I9HJAH
10. 1. 3 System Interface Information The following device information can be useful in optimizing systeminterface software. Table 13. SystemInformation String
Offset (Word Address) IBH LCH IDH LEH FH !OH !lH !2H !3H !4H !5H :6H Length OlH OlH OlH OlH OlH OlH OlH OlH OlH OIH OIH OlH V,, Logic Supply Minimum 27H (2.7V) I . Description Write/Erase voltage
I
V, Logic Supply Maximum Write/Erase voltage 55H (5.5V) V, Programming Supply Minimum Write/Erase voltage 27I.I (2.7V) V, Programming Supply Maximum Write/Erase voltage 55H (5.5V) Typical Timeout per Single Byte/Word Write 03H (23=8 usec) Typical Timeout for Maximum Size Buffer Write (32 Bytes) 03H (2%4 usec) Typical Timeout per Individual Block Erase OAH (OAH=lO , 2i"=1024 msec) Typical Timeout for Full Chip Erase OFH (OFH=15 , 2iJ=32768 msec) Maximum Timeout per Single Byte/Word Write, 2N times of typical 04H (r=16 , 8 usec x16=128 usec) Maximum Timeout Maximum Size Buffer Write, 2N times of typical 04H (24=16, 64 usec x16=1024 usec) Maximum Timeout per Individual Block Erase, 2N times of typid 04H (2'=16, 1024 msec x16=16384 msec) Maximum Timeout for Full Chip Erase, 2N times of typical 04H (24=16, 32768 msec x16=524288 msec)
T1155E.01
L
SHARP
10. 1. 4 Device Geometry
ID246 SERIES PRODUCT OVERVIEW
20
Definition
This field provides critical details of the flash device geometry.
Table 14. Device Geometry Definition
Offsel
(Word 2lH 28H. 29H 2Ali. 2CH 2DH, 2EH 2FH. 30H 2BH Address)
Length
OlH 02H 02H OlH 02H 02H
I Device Size 15H (15H=21,22'=2097152=2M
Description
Bytes
Flash Device Interface description 02H,OOH (x8/x16 supports x8 and xl6 via BYlE#) Maximum Number of Bytes in Multi word/byte 05H.OOH (2'=32 Bytes) Number of Erase Block Regions within device 01 H (symmetricatly blocked) Tbe Number of Erase Blocks lFH,OOH (lFH=31 =>31+1=32 Blocks write
The Number of "256 Bytes" cluster in a Erase block 00H,OlH (OlOOH=256 =>256 Bytes x 256=643 Bytes in a Erase Block) T1?5641
10. 1. 5 SCS OEM Specific Extended Query Table Certain flash featuresand commandsmay be optional in a vendor-specific algorithm specification. The optional vendor-specific Query table(s) may be usedto specify this and other types of information. Thesestructuresare defined solely by the flash vendor(s). Table 15. SCS OEM Specific Extended Query Table
(Word offset Address) Length 03H OlH OlH 04H PRI 50H, 52H, 49H 3 1 H (1) Major Version 30H (0) Minor Version Description
3lH,32H,33H 34H 35H 36H. 37H. 38H. 39H
Number Number,
, ASCII ASCII
OFH, OOH, OOH, COH Optional Command support bitO=l : Chip Erase Supported bitl=l : Suspend Erase Supported b&2=1 : Suspend Write Supported bit3=1 : Lock/Unlock Sqported bit4=0 : Queued Erase. Not Supported bit5-31=0 : reserved for future use. OlH Supported Functions after Suspend bitO=l : Write Supported after Erase Suspend bit l-7=0 : reserved for future use 03H, OOH Block Status Register Mask bitOr : Block Status Register Lock Bit (BSR.01 active bitl=l : Block Status Register Valid Bit [BSR.l] active biQ-15=0 : reserved for future use Vcc Logic Supply 50H (5.OV) V, Progr amming performance) 50H (5.OV) Reserved for future Optimum Supply Write/Erase Optimum voltage (highest performance)
3AH
OIH
3BH, 3CH
02H
3DH 3EH
OlH OlH
Write/Erase
voltage (highest
3FH
reserved
versions of the SCS Spccitication rrrm-ot
SHARP
10. 2 STS Configuration The RDY/BSY# Command
ID246 SERIES PRODUCT OVERVIEW
21
pin can be configured to different states using the STS Configuration command. Once the RDYI
BSY# pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or card is reset. Upon initial power-up and after exit from deep power-down RDY/BSY# that the WSM is ready for a new operation. To reconfigure the RDY/BSY# pin to other modes, the STS Configuration is issued followed by the appropriate are all pulse mode for use as a system interrupt. mode. the pin defaults to RY/BY# operation where STS low indicates that the WSM is busy. STS high indicates
configuration code. The three alternate configurations
Table 16. STS Configuration
Coding Description Effects
Set STS pin to default level mode (RY/BY#). RY/BY# in the default level-mode of operation will indicate WSM status condifion. Set STS pin to plused output signal for specific erase operation. In this mode, STS provides low pulse at the completion of Block Erase,Full Chip Erase and Clear Block Lock-bit ooeration. Set STS pin to pulsed output signal for a specific write operation. In this mode, STS provides low pulse at the completion of (multi) Byte Write and Set Block Lock-bit operation. Set STS pin to pulsed output signal for specific write and erase operation.STS provides low pulse at the completion of Block Erase, Full Chip Erase, (Multi) Word/Byte Configuration operations.
T1158E-01
Table 17. Write Protection Alternatives
Operation
I
Block Erase, (Multi) Word/Byte Write
Block Lock-Bit 0 1
L
BLKEN bit of Write Protection Resister h
Effect
I
I
I
Full Chip Erase
CL1 X X X
Set Block Lock-Bit Clear Block Lock-Bits
1Block Erase and (Multi) Word/Byte Write Enabled. 1Block is Locked. Block Erase and (Multi) Word/Byte Write Disabled. Block Lock-Bit Override. Block Erase and (Multi) Word/Byte Write Enabled. All unlocked blocks are erased, lockd blocks are not erased. All Block Lock-Bit Disabled. Set Block Lock-Bit Disabled. Set Block Lock-Bit Enabled. Clear Block Lock-Bit Disabled. Clear Block Lock-Bit Enabled. T1159E01
SHARP
11. Electrical Specifications
Maximum Ratings 11. 1 Absolute
ID246 SERIES PRODUCT
OVERVIEW
22
PARAMETER r Supply Voltage 1Program Voltage ~Input Voltage Operating Temperature 1 Storage Temperature 1
NOTE 2 2 2 1
SYMBOL V cc V PP vm T OPFC TSTG
RATING -0.3 to 6.0 -0.2 to 7.0 -0.3 to Vcc+0.3(Max:6.0) 0 to 60 -20 to 65
UNIT V V V `C `c T1165E41
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. All specified voltages are with respect to GND. During transitions, this level may undershoot to -2.0~ for periods c20ns or overshoot to Vcc+2.Ov for periods <20ns. 11.2 Recommended Operating Coriditions
T1177E-01
11. 3 Capacitance Ta=25 "c , f= 1MHz PARAMETER Input Capacitance Input/Output Capacitance SYMBOL GIN 50 MIN TYP 15 25 MAX UNIT PF PF CONDITION v,,=o.ov vo,=o.ov
11.4
AC Input/Output
Test Conditions
Figure 5. Transient Input/Output Reference Waveform Figure 5 shows Input/Output level and test level for AC test. Input rise and fall times (10% to 90%) < Ions.
ID246 SERIES PRODUCT
OVERVIEW
23
12. DC Characteristics
(Ta=Oto6O"C) PARAMETER TEST CONDITION
Output High Voltage
Vcc Read Current
(Continue
to next page)
T1166E.01
SHARP
DC Characteristics (Continued)
SYMBOL
ID246 SERLES PRODUCT
OVERVIEW
24
(Ta = 0 to 60C) TEST CONDITION
V, Stand-by or Read
V, DeepPower-Down Current V,, Word Write or Set Lock-Bit Current V,, Block Erase or ClearLock-Bit Current 40MB V, Word Write or I Block Erase Suspend PPWS 6 4PES Current 48MB 32MB 40MB 48MB V,, LockoutVoltage NOTE: 1. Theseparametersare applied to all input pins and all input/output pins in input mode. 2. Theseparametersare applied to AO-& and D,-Dn in input mode and RESET. 3. Theseparametersare applied to CE,#,CE,#,WB#,OE# and REG#. 4. Theseparametersare applied to RDY/BSY#. 5. Theseparametersare applied to D,-DrS in output mode. 6. All currentsare in RMS unlessotherwise notes. 7. Block erase,word/byte write, and lock-bit configurations are inhibited when V,s the V, Voltage is Vpp,, or V,. 8. Sampled. V,,, and guaranteedin V 78 -EL!5 520 5.50 1.6 2.0 2.4 1.5 1.5 520 550 ,uA ,u A mA mA mA v
Tl lC7E-01
V&Vcc
v+vcc
CPS0008E-00
SHARP
13. AC Characteristics
Testing Conditions : 1) Input Pulse Level 2) Input Rise/Fall Time
ID246 SERIES PRODUCT
OVERVIEW
25
1.5 to 3.5v (@vcc=5vk5%,vcc=5v~lo%) 0 to 3.ov (@Vcc=3.3kOo.3V) 1Ons 2.5V (@Vcc=5V+5%,Vcc=5V+1oQ) 1.5v (@Vcc=3.3V&.3V) I-I-l-L,+lOOpF ( @VCC=~V+~%,VCC=~V~IO%) Il-I-L+SOpF (@Vcc=3.3V+O.3V)
3) Input/Output Timing Reference Level
4) Output Load (including scope and jig capacitance)
13. 1 Common
,
Memory
Read Operations ---- -BOL vcc=3.3v+ 0.3v Vcc=SVk 5% 1 vcc=sv
(Ta = 0 to 60C) + 10% [Jnit
ns
*:Time until output becomes floating. (The output voltage is not defined.)
TlC43-01
SHARP
ID246 SERIES PRODUCT OVERVIEW
1
tFl
*
Address
w
t(A) \ 4 to3
e
* /
b(A)
w
CE#, CE2#
/
////
OE#
Dout
Figure 6. AC Waveforms for ReadOperations
Note) 1. WE# = "HIGH", during a read cycle. 2. Either "HIGH" or "LOW" in diagonal areas. 3. The output data becomesvalid when last interval, ta (A), ta (CE) or ta (OE) have concluded.
SHARP
13.2 Command Write Operations
ID246 SERIES PRODUCT
OVERVIEW
27
: Common
Memory
13. 2. 1 WE# Controlled
Write Operations (Vcc=3.3VrtD.3\ Ta=Oto 60C) I,
PARAMETER Write Cycle Time Address Setup Time Write Recovery Time Data Setup Time for WE# Data Hold Time OE# Hold Time from WE# CE# Setup Time for WE# Address WE# Setup Time for
SYMBOL IEEE 1
PCMCIA
CONDITION I I
vcc=3.3v -tn ?V .".a v MIN 250 30 I MAX
Unit
t*"A-J trW
ns ns
Write Pulse Width WE# High to RDY/BSY# going Low RESET Recovery Time V, Setun Time V, Hold Time Word/Byte Write Time
Block Erase Time Set Lock-Bit Time
V,,=3.3VkO.3% fwHQ"4 v,,=5v+lo% V,,=3.3V~.3% v,,=w *lo% vPP=3.3vti.3% v,*=5v *lo% 10.0 10.0 9.3 21.1 17.2
S
Clear Block Lock-Bits Time
Word/Byte Suspend Latency $IHRHI Time to Read Erase Suspend Latency Tie to Read
PS /IS PS P's
T1168E-01
SHARP
ID246 SERIES PRODUCT
OVERVIEW
(Vcc=SVfi%, PARAMETER
Vcc=5V+lO%,,
Ta = 0 t 60C )
~ Unit
~ ns 1 ns ns ns ns
OE# Hold Time from
ns ns ns ns ns P's ns ns PS
S
PS Clear Block Lock-Bits
S
Erase Suspend Latency Tie to Read
1169E-01
CPSCW~E~IO
SHARP
ID246 SERIES PRODUCT
OVERVIEW
Vu Wkl VU
VIII VU
t1 I
I
th(oE-w-l!)
WHQVLZ.3.4 , I-
\
u
3
DATA VU WtIRHI.2
VOH
RDY/BSY# RESET
I
h I
E -4
VU
VW12
/
I I
VPP VU
1. 2. 3. 4. 5. 6.
V,. POWER-UP AND STANDBY WRITE DATA WRITE OR ERASE SETUP COMMAND WRITE VALID ADDRESS AND DATA OR ERASE COMFIRM AUTOMATED DATA WRITE OR ERASE DELAY READ STATUS REGISTER DATA WRtTE READ ARRAY COMMAND
COMMAND
FIOIC-03
Figure 7.
Note)
AC Waveforms
for Write Operations (WE# Controlled)
While the data signalis in output mode, do not apply an oppositephaseinput signal.
SHARP
13. 2. 2 CE# Controlled
ID246 SERIES PRODUCT
OVERVIEW
Write Operations
(Vcc=3,3V ti.3V,
Ta = 0 to 60C )
Erase Suspend Latency Tie
T1170E-01
SHARP
ID246 SERIES PRODUCT OVERVIEW
31
PARAMETER Write Cycle Time AddressSetup Time Write Recovery Time Data Setup Time for CE# Data Hold Time
IEEE t LIZ bvEH
I'"VIIBOL `Yb --_ _--.
KMCIA
(Vcc=SV Y%, Vcc=SV MO%, Ta=Oto 60C ) vcc=sv +-lo% vcc=sv Y% CONDITION Unit . I... . I. wr . . ..I I,.., I
t A".%"
&HDx OE# Hold Time from CE# acL
W)
I
Write Pulse Width CE# High to RDY/BSY# going LO*
b.EH
t (cm
I
1
80
1
-
1
80
I
-
I
ns I
_ hHRL
1 - ( 1401 - 1 1401 ns 1
I
Clear Block Lock-Bits Time
I kHQV.4
LRHl
I
v,=w *lo% 7.0 7.0 ps
Word/Byte Suspend Latency Time to Read Erase Suspend Latency Tie to Read
v,,=5v *lo%
13.1
-
13.1
#us
T1171EQl
SHARP
ID246 SERIES PRODUCT OVERVIEW
32
1. Address
2.
AIN
3.
4.
5.
6.
WE# VIL
VIII VIII OEX VU
hi 31#, cm VU.
tdA)-
I
b
MOE-C'3
4
hWE-CEH)
i)-
e
lEHQVI.23.4
VOH
I I I
tDYlJsY#
VOL VIII
RESET
VLL
VPPl.2 VPP VU 1. 2. 3. 4. 5. 6. Vcc POWER-UP AND STANDBY WRITr DATA WRITE OR ERASE SETUP COMMAND WRITE VALID ADDRESS AND DATA OR ERASE COhtFlRh4 AUTOMATED DATA WRlTE OR ERASE DELAY READ STATUS REGISTER DATA WRITE READ ARRAY COMMAND
COMMAND
Figure 8.
AC Waveforms for Write Operations (CE# Controlled)
Note) While the data signal is in output mode, do not apply an opposite phase input signal.
SHARP
ID246 SERIES PRODUCT
OVERVIEW
33
13. 3 Attribute Memory Read Operation
(Ta=O-60C) PARAMETER Read Cycle Time Address Access Tie CE# Access Time OE# AccessTime Output DisableTime from CEl#,CE2# * Output DisableTime from CE# Output DisableTime from CE 1#,CE2# Output DisableTime from OE# SYMBOL IEEE tAVAV t *w-w
PCMCIA
Vcc=3.3Vf MIN 600 -
0.3v MAX 600
600 I
vcc=sv MM 300 -
AZ 10% MAX 300 300 150 100 100 -
Unil
tcR L(A)
wm
~ tm.Qv fGLQV
t t Ew2 GHPZ
WEI fdir(CE) MOE) Mm
5
300 150 150 -
5
ns
fn ON7
Data Valid Tie from AddressChange
1
i t&9
I
IOI-Iol-I
I
I
I
I
I
* : Tie until becomes floating.(Theoutputvoltageis notdefined)
T1056-G
Note) When the CIS constructedby EEPROM, this card requires 5V voltage for Vcc.
Address
CEl#, CE2#
OE# I L&E) 4 Dout High-Inpedance ta(OE) ,.j )
/ tdis(OE) ._
I / * hiiKE) \\) /I/
DataOutputisvalid
Figure 9.
Attribute Memory Read Operation
CPSCWXE-001
SHARP
ID246 SERIES PRODUCT
OVERVIEW
34
13. 4 Attribute Memory Write Operation
(Ta=O-60C) SYMBOL IEEE
t AVAV
vcc=3.3v f 0.3v
I
vcc=5vt
I
1070
I
1
I t
CW
PCMCIA
MIN
1 MAX I 1 -
MIN
1 MAX I -
Unit ns ns ns
I
1 600 70 150 70
1 250 30 80 30 150
i Address Setup Time ~ Write Recovery Time 1 data Setup Time i Data Hold Time /Address SetupTime for WE# 1 Write Pulse Width Setup Time for OE# Hold Tie for OE# Setup Tie for CE# Hold Time for CE#
T1057.01
LlAx
t DVWH L UnY
L(WE)
`a@-WEH) k@)
Note) When the CIS constructed by EEPROM, this card requires 5V voltage for Vcc.
Address
CEl#, CE2#
OE#
WE#
DATA
F1057-01
Figure 10. Attribute
Memory Write Operation
SHARP
13.5 Power-Up/Power Down
ID246 SERIES PRODUCT OVERVIEW
PARAMETER CE# Signal Level (O.OV < Vcc < 2.OV) CE# Signal Level (2.OV c Vcc c VIH) CE# Signal Level (VIH c Vcc) CE# Setuo Time RESET SetupTime CE# Recover Time
VCC Rising Time
SYMBOL PCMCIA Vi (CE)
NOTES 1 1 1
/
MIN 0 vcc-o. 1 VU4 20 20
/
MAX ViMAX Vih4AX Vih4AX -
/
UNITS V V V ms ms
/
L" WCC) tsu(RESET)
-
VCCFalling Time RESET Width RESET Width RESET Width tb (Hi-Z RESET) ts (Hi-Z RESET) 1 0 ms ms
NOTES: 1. VM~ meansAbsolute Maximum Voltage for input in the period of O.OV < Vcc < 2.0 V, Vi (CE#) is only o.oov-v&fAx 2. The tDrand tpf are defined as "linear waveforms" in the period of 10% to 9010, or vice-versa. Even if the waveform is not a "liner waveform," its rising and falling ime must meet this specification.
---
tsu (RESET)
=
t,,(Hi-z RESET)
Hi-Z-----------
3E1# yz5jK-J
ts(Hi-Z RESET) -------------_
Hi-Z
F1012-01
Figure Il.
Power-Up/Down Timing
i
SHARP
14. Specification Changes
ID246 SERIES PRODUCT OVERVIEW
This datasheet is for ID246 series product overview, and final specifications will be submitted for qualification of the memory card. Please note that contents of this datasheet may be revised without announcement beforehand. Please do NOT finalize a system design with this information.
15. Other Precautions
. Permanent damage occurs if the memory card is stressed beyond Absolute Maximum beyond the Recommended Recommended Operating Conditions may affect device reliability. . Writing to the memory card can be prevented by switching memory card. . Avoid allowing the memory card connectors to come in contact with metals and avoid touching the connectors, as the internal circuits can be-damaged by static electricity. + Avoid storing in direct sunlight, high temperatures (do not place near heaters or radiators), high humidity and dusty areas. . . . Avoid subjecting the memory card to strong physical abuse. Dropping, bending, smashing or throwing the card can result in loss of function. When the memory card is not being used, return it to its protective case. Do not allow the memory card to come in contact with fire. on the write protect switch on the end of the Ratings. Operation Operating Conditions is not recommended and extended exposure beyond the
SHARP
ID246 SERIES PRODUCT
OVERVIEW
I
A 0
ENLARGEMENT WR I TE-PROTECT
OF
THE SW ITCH
16. External
Diagrams
Back
935
t68 6kO.l
onncc Area) 3. 3 f0. t \ 1w
Protected
50. 8 1. 6
1.
b,,
II -
50.
8
.
I
" C
_I.
II
(Substrate
Area)
(fubrtrate
Area)
4 n a
-
1.
1
51.
8
I
\&
\2-R2
51. cS"btrOtc Area)
8
FRONT
BACK
1.
51 III
41.
3
TIIICKNESS
tlATERIAL
FINISH NAME
MEMORY EXTERNAL
CAR0 DIAGRAM
CPSWOGE-00

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